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【工作机会】Staff Engineer – Digital and Mixed-Signal Des
[版面:招聘/求职][首篇作者:shadingyu] , 2019年07月30日13:29:13 ,102次阅读,0次回复
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发信人: shadingyu (fish), 信区: JobMarket
标  题: 【工作机会】Staff Engineer – Digital and Mixed-Signal Desi (转载)
发信站: BBS 未名空间站 (Tue Jul 30 13:29:13 2019, 美东)

【 以下文字转载自 JobHunting 讨论区 】
发信人: shadingyu (fish), 信区: JobHunting
标  题: 【工作机会】Staff Engineer – Digital and Mixed-Signal Design- Portland
发信站: BBS 未名空间站 (Tue Jul 30 13:27:56 2019, 美东)

Staff Engineer – Digital and Mixed-Signal Design- in Portland

Experience:
• MSEE or PHD with minimum of 6+ years experience in deep sub-micron
mixed signal design
• High speed digital PMA/PCS design experience including one or more
of the following PHY architecture: Serdes, DDRx, LPDDRx or RF.
• Knowledge & hands-on experience with one or more of the following IO
protocols: PCIe, SATA, USB, SGMII, CEI, FC, Interlaken, XAUI, XPON, DDR3/4,
LPDDR3/4, Intel PIPE 3.0 or above.
• Knowledge and hands-on experience on digital physical media
attachment (DPMA) from architecture definition, RTL coding, logic & mixed
signal verification, IP collateral generation, to post-silicon validation at
both component & system level.
• A track record in delivering high volume commercial products from
architecture definition to post-silicon product qualification, & working
knowledge in industry best practices
• Previous experience in TSMC/UMC’s 40nm process or more advanced
node and Hard
IP’s SoC/system integration & validation flow is a strong plus.
• Past experience in supporting deal acquisition and external customer
engagement is a must.

Skill:
• Strong fundamental in digital, mixed signal and ASIC design &
verification.
• Strong coding skill in Perl, C, Verilog, System Verilog. Past
experience with Python, Verilog-AMS, Verilog-A is a strong plus.
• Experience with tools/flows such as VCS, Design/RTL compiler,
Formality, CDC,
Discovery-AMS, LINT, UVM/OVM/VMM, B-scan, UPF & Scan/BIST , DFT, FPGA flow.
• Past experience with one of more of the following buses: I2C, AMBA
AXI/APB/AHB, PCS, TAP/JTAG, Boundary scan, Memory-mapped-IO,
• Knowledge in digital signal processing, control theory, system
behavior modeling, power management & power-up sequence, clocking and data
pipeline/latency, and IO’s training algorithm is a strong plus
• Knowledge of Physical implementation flows, such as Synthesis, floor
-planning, design constrain, CTS, ICC, design/timing convergence, and
reliability flows.
• Creative design and problem solving ability delivering the highest
level result across power, performance and area
• Strong communication and presentation skills. Ability to work
independently with local and international teams under different time zone
and language background.
• Ability to work across all functional levels. Highly disciplined and
self-motivated. Able to support occasional domestic or international travel
per business requirement.

请站内或者Email [email protected]
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